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@ -28,10 +28,10 @@ along with VP-Digi. If not, see <http://www.gnu.org/licenses/>. |
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* Configuration for PLL-based data carrier detection |
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* DCD_MAXPULSE is the maximum value of the DCD pulse counter |
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* DCD_THRES is the threshold value of the DCD pulse counter. When reached the input signal is assumed to be valid |
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* DCD_MAXPULSE and DCD_THRES difference sets the DCD "intertia" so that the DCD state won't change rapidly when a valid signal is present |
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* DCD_MAXPULSE and DCD_THRES difference sets the DCD "inertia" so that the DCD state won't change rapidly when a valid signal is present |
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* DCD_DEC is the DCD pulse counter decrementation value when symbol changes too far from PLL counter zero |
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* DCD_INC is the DCD pulse counter incrementation value when symbol changes near the PLL counter zero |
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* DCD_PLLTUNE is the DCD tining coefficient when symbol changes, pll_counter = pll_counter * DCD_PLLTUNE |
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* DCD_PLLTUNE is the DCD timing coefficient when symbol changes, pll_counter = pll_counter * DCD_PLLTUNE |
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* The DCD mechanism is described in afsk_demod(). |
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* All values were selected by trial and error |
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*/ |
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@ -58,7 +58,7 @@ struct ModState |
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{ |
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TxTestMode txTestState; //current TX test mode |
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uint16_t dacSine[DACSINELEN]; //sine samples for DAC |
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uint8_t dacSineIdx; //current sine smaple index |
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uint8_t dacSineIdx; //current sine sample index |
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uint16_t samples_oversampling[4]; //very raw received samples, filled directly by DMA |
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uint8_t currentSymbol; //current symbol for NRZI encoding |
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uint16_t txDelay; //TXDelay length in number of bytes |
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@ -370,7 +370,7 @@ static int32_t afsk_demod(int16_t sample, Demod *dem) |
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//PLL timer is counting up and eventually overflows to a minimal negative value |
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//so it crosses zero in the middle |
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//tone change should happen somewhere near this zero-crossing (in ideal case of exactly same TX and RX baudrates) |
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//nothing is ideal, so we need to have some region around zero where the tone should change |
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//nothing is ideal, so we need to have some region around zero where tone change is expected |
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//if tone changed inside this region, then we add something to the DCD pulse counter (and adjust counter phase for the counter to be closer to 0) |
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//if tone changes outside this region, then we subtract something from the DCD pulse counter |
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//if some DCD pulse threshold is reached, then we claim that the incoming signal is correct and set DCD flag |
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@ -383,7 +383,7 @@ static int32_t afsk_demod(int16_t sample, Demod *dem) |
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if(dcdSymbol != dem->dcdLastSymbol) //tone changed |
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{ |
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if(abs(dem->dcdPll) < PLLINC) //tone change occured near zero |
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if(abs(dem->dcdPll) < PLLINC) //tone change occurred near zero |
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dem->dcdCounter += DCD_INC; //increase DCD counter |
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else //tone change occurred far from zero |
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{ |
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@ -582,6 +582,8 @@ void Afsk_transmitStop(void) |
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NVIC_EnableIRQ(DMA1_Channel2_IRQn); |
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afsk_ptt(0); |
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TIM4->CCR1 = 44; //set around 50% duty cycle |
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} |
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/** |
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@ -665,7 +667,7 @@ void Afsk_init(void) |
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DMA1_Channel2->CCR |= DMA_CCR_PSIZE_0; |
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DMA1_Channel2->CCR &= ~DMA_CCR_PSIZE_1; |
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_CIRC| DMA_CCR_TCIE; //circural mode, memory increment and interrupt |
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_CIRC| DMA_CCR_TCIE; //circular mode, memory increment and interrupt |
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DMA1_Channel2->CNDTR = 4; //4 samples |
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DMA1_Channel2->CPAR = (uint32_t)&(ADC1->DR); //ADC data register address |
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DMA1_Channel2->CMAR = (uint32_t)modState.samples_oversampling; //sample buffer address |
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