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400 lines
14 KiB
400 lines
14 KiB
/*
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Copyright 2020-2025 Piotr Wilkon
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This file is part of VP-Digi.
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VP-Digi is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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VP-Digi is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DRIVERS_MODEM_LL_STM32F302_H_
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#define DRIVERS_MODEM_LL_STM32F302_H_
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#if defined(STM32F302xC)
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#define USE_FPU 1 /**< Use FPU - F302 has one */
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#define MODEM_LL_DAC_MAX 4095 /**< Maximum value for DAC - 4095 for 12-bit DAC */
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#include <stdint.h>
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#include "stm32f3xx.h"
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/**
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* TIM1 is used for pushing samples to DAC (clocked at 18 MHz)
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* TIM3 is the baudrate generator for TX (clocked at 18 MHz)
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* TIM2 is the RX sampling timer with no software interrupt, but it directly calls DMA
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*/
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#define MODEM_LL_DMA_INTERRUPT_HANDLER DMA1_Channel2_IRQHandler
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#define MODEM_LL_DAC_INTERRUPT_HANDLER TIM1_UP_TIM16_IRQHandler
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#define MODEM_LL_BAUDRATE_TIMER_INTERRUPT_HANDLER TIM3_IRQHandler
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#define MODEM_LL_DMA_IRQ DMA1_Channel2_IRQn
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#define MODEM_LL_DAC_IRQ TIM1_UP_TIM16_IRQn
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#define MODEM_LL_BAUDRATE_TIMER_IRQ TIM3_IRQn
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#define MODEM_LL_DMA_TRANSFER_COMPLETE_FLAG (DMA1->ISR & DMA_ISR_TCIF2)
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#define MODEM_LL_DMA_CLEAR_TRANSFER_COMPLETE_FLAG() (DMA1->IFCR |= DMA_IFCR_CTCIF2)
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#define MODEM_LL_BAUDRATE_TIMER_CLEAR_INTERRUPT_FLAG() (TIM3->SR &= ~TIM_SR_UIF)
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#define MODEM_LL_BAUDRATE_TIMER_ENABLE() (TIM3->CR1 = TIM_CR1_CEN)
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#define MODEM_LL_BAUDRATE_TIMER_DISABLE() (TIM3->CR1 &= ~TIM_CR1_CEN)
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#define MODEM_LL_BAUDRATE_TIMER_SET_RELOAD_VALUE(val) (TIM3->ARR = (val))
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#define MODEM_LL_DAC_TIMER_CLEAR_INTERRUPT_FLAG (TIM1->SR &= ~TIM_SR_UIF)
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#define MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(val) (TIM1->ARR = (val))
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#define MODEM_LL_DAC_TIMER_SET_CURRENT_VALUE(val) (TIM1->CNT = (val))
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#define MODEM_LL_DAC_TIMER_ENABLE() (TIM1->CR1 |= TIM_CR1_CEN)
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#define MODEM_LL_DAC_TIMER_DISABLE() (TIM1->CR1 &= ~TIM_CR1_CEN)
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#define MODEM_LL_ADC_TIMER_ENABLE() (TIM2->CR1 |= TIM_CR1_CEN)
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#define MODEM_LL_ADC_TIMER_DISABLE() (TIM2->CR1 &= ~TIM_CR1_CEN)
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#define MODEM_LL_DAC_PUT_VALUE(value) (DAC1->DHR12R1 = (value))
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static inline void MODEM_LL_DCD_LED_ON(void)
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{
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GPIOB->BSRR = GPIO_BSRR_BR_8;
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GPIOB->BSRR = GPIO_BSRR_BS_9;
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}
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static inline void MODEM_LL_DCD_LED_OFF(void)
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{
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GPIOB->BSRR = GPIO_BSRR_BR_8;
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GPIOB->BSRR = GPIO_BSRR_BR_9;
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}
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#define MODEM_LL_SET_TX_ATTENUATOR(state) (GPIOA->BSRR = (state ? GPIO_BSRR_BR_3 : GPIO_BSRR_BS_3))
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/**
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* @brief Enable PTT
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* @param output Output number (AIOC only, meaningless on other platforms)
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*/
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static inline void MODEM_LL_PTT_ON(uint8_t output)
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{
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GPIOB->BSRR = GPIO_BSRR_BR_9;
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GPIOB->BSRR = GPIO_BSRR_BS_8;
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switch (output)
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{
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case 0:
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GPIOA->BSRR = GPIO_BSRR_BS_0;
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break;
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case 1:
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GPIOA->BSRR = GPIO_BSRR_BS_1;
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break;
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}
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}
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/**
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* @brief Enable PTT
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* @param output Output number (AIOC only, meaningless on other platforms)
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*/
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static inline void MODEM_LL_PTT_OFF(uint8_t output)
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{
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GPIOB->BSRR = GPIO_BSRR_BR_8;
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GPIOB->BSRR = GPIO_BSRR_BR_9;
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switch (output)
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{
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case 0:
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GPIOA->BSRR = GPIO_BSRR_BR_0;
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break;
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case 1:
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GPIOA->BSRR = GPIO_BSRR_BR_1;
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break;
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}
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}
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/**
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* @brief Initialize clocks
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*/
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static void MODEM_LL_INITIALIZE_RCC(void)
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{
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
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RCC->AHBENR |= RCC_AHBENR_ADC12EN;
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RCC->APB1ENR |= RCC_APB1ENR_DAC1EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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}
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/**
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* @brief Initialize PTT outputs and LEDs
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*/
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static void MODEM_LL_INITIALIZE_OUTPUTS(void)
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{
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/* DCD and PTT LEDs: between PB8 and PB9 */
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GPIOB->MODER &= ~GPIO_MODER_MODER8;
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GPIOB->MODER |= GPIO_MODER_MODER8_0;
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GPIOB->OTYPER &= ~GPIO_OTYPER_OT_8;
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GPIOB->BSRR = GPIO_BSRR_BR_8;
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GPIOB->MODER &= ~GPIO_MODER_MODER9;
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GPIOB->MODER |= GPIO_MODER_MODER9_0;
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GPIOB->OTYPER &= ~GPIO_OTYPER_OT_9;
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GPIOB->BSRR = GPIO_BSRR_BR_9;
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/* PTT: PA0, PA1 */
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GPIOA->MODER &= ~GPIO_MODER_MODER0;
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GPIOA->MODER |= GPIO_MODER_MODER0_0;
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_0;
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GPIOA->BSRR = GPIO_BSRR_BR_0;
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GPIOA->MODER &= ~GPIO_MODER_MODER1;
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GPIOA->MODER |= GPIO_MODER_MODER1_0;
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_1;
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GPIOA->BSRR = GPIO_BSRR_BR_1;
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/* PA3: open-drain TX attenuator */
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GPIOA->MODER &= ~GPIO_MODER_MODER3;
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GPIOA->MODER |= GPIO_MODER_MODER3_0;
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GPIOA->OTYPER |= GPIO_OTYPER_OT_3;
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GPIOA->BSRR = GPIO_BSRR_BS_3; //open drain = no attenuation by default
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}
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/**
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* @brief Set RX gain
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* @param gain New RX gain: 1, 2, 4, 8 or 16
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* @note Invalid values have no effect
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* @note Only used for AIOC rev. >= 1.2, has no effect on other platforms
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*/
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static void MODEM_LL_SET_GAIN(uint8_t gain)
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{
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switch(gain)
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{
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case 1:
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//adc gain=1, switch to follower mode later
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OPAMP2->CSR &= ~OPAMP_CSR_PGGAIN; //bias gain=16
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OPAMP2->CSR |= OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1;
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break;
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case 2:
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OPAMP2->CSR &= ~OPAMP_CSR_PGGAIN; //bias gain=8
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OPAMP2->CSR |= OPAMP_CSR_PGGAIN_1;
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OPAMP1->CSR &= ~OPAMP_CSR_PGGAIN; //adc gain=2
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//3.3%*2*8=52.8%
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break;
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case 4:
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OPAMP2->CSR &= ~OPAMP_CSR_PGGAIN; //bias gain=4
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OPAMP2->CSR |= OPAMP_CSR_PGGAIN_0;
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OPAMP1->CSR &= ~OPAMP_CSR_PGGAIN; //adc gain=4
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OPAMP1->CSR |= OPAMP_CSR_PGGAIN_0;
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//3.3%*4*4=52.8%
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break;
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case 8:
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OPAMP2->CSR &= ~OPAMP_CSR_PGGAIN; //bias gain=2
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OPAMP1->CSR &= ~OPAMP_CSR_PGGAIN; //adc gain=8
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OPAMP1->CSR |= OPAMP_CSR_PGGAIN_1;
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//3.3%*8*2=52.8%
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break;
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case 16:
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//bias gain=1, switch to follower mode later
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OPAMP1->CSR &= ~OPAMP_CSR_PGGAIN; //adc gain=16
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OPAMP1->CSR |= OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1;
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//3.3%*16*1=52.8%
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break;
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default:
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return;
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}
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if(1 == gain)
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{
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//adc gain at 1 (follower), bias gain at 16 (just enable PGA here)
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OPAMP1->CSR |= OPAMP_CSR_VMSEL;
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OPAMP2->CSR &= ~OPAMP_CSR_VMSEL;
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OPAMP2->CSR |= OPAMP_CSR_VMSEL_1;
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}
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else if(16 == gain)
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{
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//adc gain at 16 (just enable PGA here), bias gain at 1 (follower)
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OPAMP1->CSR &= ~OPAMP_CSR_VMSEL;
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OPAMP1->CSR |= OPAMP_CSR_VMSEL_1;
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OPAMP2->CSR |= OPAMP_CSR_VMSEL;
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}
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else
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{
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//in any other case, enable PGA on both op amps
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OPAMP1->CSR &= ~OPAMP_CSR_VMSEL;
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OPAMP1->CSR |= OPAMP_CSR_VMSEL_1;
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OPAMP2->CSR &= ~OPAMP_CSR_VMSEL;
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OPAMP2->CSR |= OPAMP_CSR_VMSEL_1;
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}
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}
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/**
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* @brief Initialize ADC
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* @return Utilized ADC pointer
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*/
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static volatile ADC_TypeDef* MODEM_LL_INITIALIZE_ADC(int32_t *bias)
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{
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//OPAMP2 as ADC bias generator
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OPAMP2->CSR |= OPAMP_CSR_FORCEVP; //reference voltage as non-inverting input
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OPAMP2->CSR &= ~OPAMP_CSR_VMSEL; //programmable gain amplifier mode
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OPAMP2->CSR |= OPAMP_CSR_VMSEL_1;
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OPAMP2->CSR &= ~OPAMP_CSR_CALSEL; //reference = 3.3% VDDA
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OPAMP2->CSR &= ~OPAMP_CSR_PGGAIN; //x16 gain to get 52.8% VDDA bias
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OPAMP2->CSR |= OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1;
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OPAMP2->CSR &= ~OPAMP_CSR_TSTREF; //make sure reference voltage is enabled
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OPAMP2->CSR |= OPAMP_CSR_OPAMPxEN; //enable op amp
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//OPAMP1 as ADC preamp
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OPAMP1->CSR &= ~OPAMP_CSR_FORCEVP; //make sure reference voltage is not used
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OPAMP1->CSR &= ~OPAMP_CSR_VPSEL_1; //PA5 (signal input) as non-inverting inptu
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OPAMP1->CSR |= OPAMP_CSR_VPSEL_0;
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OPAMP1->CSR |= OPAMP_CSR_VMSEL; //input follower mode for now
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OPAMP1->CSR |= OPAMP_CSR_OPAMPxEN; //enable op amp
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MODEM_LL_SET_GAIN(1);
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/* ADC input: PB2 (ADC2 channel 12) or PA5 via OPAMP1 (ADC1 channel 3) */
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GPIOB->MODER |= GPIO_MODER_MODER2;
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GPIOA->MODER |= GPIO_MODER_MODER5;
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/*/4 prescaler */
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RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
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RCC->CFGR2 |= RCC_CFGR2_ADCPRE12_DIV4;
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//configure ADC1 channel 3 first and check if there is bias (AIOC rev. >= 1.2)
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ADC1->CFGR |= ADC_CFGR_CONT;
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ADC1->CFGR &= ~ADC_CFGR_EXTEN;
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/* 61.5 cycle sampling = 292 kHz */
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ADC1->SMPR1 &= ~ADC_SMPR1_SMP3;
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ADC1->SMPR1 |= ADC_SMPR1_SMP3_2 | ADC_SMPR1_SMP3_0;
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ADC1->SQR1 &= ~ADC_SQR1_SQ1;
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ADC1->SQR1 |= (3 << ADC_SQR1_SQ1_Pos); //channel 3
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ADC1->SQR1 &= ~ADC_SQR1_L; //single conversion
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ADC1->DIFSEL &= ~ADC_DIFSEL_DIFSEL_3;
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/* Enable voltage regulator and perform calibration */
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ADC1->CR &= ~ADC_CR_ADVREGEN;
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ADC1->CR |= ADC_CR_ADVREGEN_0;
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HAL_Delay(20);
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ADC1->CR &= ~ADC_CR_ADCALDIF;
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ADC1->CR |= ADC_CR_ADCAL;
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while(ADC1->CR & ADC_CR_ADCAL)
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;
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HAL_Delay(20);
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/* Enable ADC */
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ADC1->CR |= ADC_CR_ADEN;
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while(!(ADC1->ISR & ADC_ISR_ADRDY))
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;
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ADC1->CR |= ADC_CR_ADSTART;
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*bias = 4325; //ADC bias is around 4325, because the opamp generates the bias at 3.3%*16=52.8% of VDDA
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//collect some samples and average them
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ADC1->DR;
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uint32_t sum = 0;
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for(uint8_t i = 0; i < 16; i++)
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{
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while(!(ADC1->ISR & ADC_ISR_EOC))
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;
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sum += ADC1->DR;
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}
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sum /= 16;
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//check whether the average is between 40% and 60% of the ADC range, that is, whether there is a proper bias present
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if((sum < (uint32_t)(0.4f * 4096.f)) || ((sum > (uint32_t)(0.6f * 4096.f))))
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{
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//if not, disable ADC1 and set up ADC2 (old AIOC revision)
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ADC1->CR |= ADC_CR_ADSTP;
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while(ADC1->CR & ADC_CR_ADSTP)
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;
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ADC1->CR |= ADC_CR_ADDIS;
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ADC2->CFGR |= ADC_CFGR_CONT;
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ADC2->CFGR &= ~ADC_CFGR_EXTEN;
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/* 61.5 cycle sampling = 292 kHz */
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ADC2->SMPR2 &= ~ADC_SMPR2_SMP12;
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ADC2->SMPR2 |= ADC_SMPR2_SMP12_2 | ADC_SMPR2_SMP12_0;
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ADC2->SQR1 &= ~ADC_SQR1_SQ1;
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ADC2->SQR1 |= (12 << ADC_SQR1_SQ1_Pos); //channel 12
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ADC2->SQR1 &= ~ADC_SQR1_L; //single conversion
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ADC2->DIFSEL &= ~ADC_DIFSEL_DIFSEL_12;
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/* Enable voltage regulator and perform calibration */
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ADC2->CR &= ~ADC_CR_ADVREGEN;
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ADC2->CR |= ADC_CR_ADVREGEN_0;
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HAL_Delay(20);
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ADC2->CR &= ~ADC_CR_ADCALDIF;
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ADC2->CR |= ADC_CR_ADCAL;
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while(ADC2->CR & ADC_CR_ADCAL)
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;
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/* Enable ADC */
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ADC2->CR |= ADC_CR_ADEN;
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while(!(ADC2->ISR & ADC_ISR_ADRDY))
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;
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ADC2->CR |= ADC_CR_ADSTART;
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*bias = 4095; //assume bias to be in the middle in old AIOC revision
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return ADC2;
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}
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else
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return ADC1;
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}
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/**
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* @brief Initialize DMA
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* @param *buffer Target memory buffer
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* @param count Number of words to be copied
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* @param *adc Source ADC
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*/
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static void MODEM_LL_INITIALIZE_DMA(volatile void *buffer, uint16_t count, volatile ADC_TypeDef *adc)
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{
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/* 16 bit memory region */
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DMA1_Channel2->CCR |= DMA_CCR_MSIZE_0;
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DMA1_Channel2->CCR &= ~DMA_CCR_MSIZE_1;
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DMA1_Channel2->CCR |= DMA_CCR_PSIZE_0;
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DMA1_Channel2->CCR &= ~DMA_CCR_PSIZE_1;
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/* Enable memory pointer increment, circular mode and interrupt generation */
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_TCIE;
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DMA1_Channel2->CNDTR = count;
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DMA1_Channel2->CPAR = (uintptr_t)&(adc->DR);
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DMA1_Channel2->CMAR = (uintptr_t)(buffer);
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DMA1_Channel2->CCR |= DMA_CCR_EN;
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}
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/**
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* @brief Initialize primary DAC
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*/
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static void MODEM_LL_INITIALIZE_DAC(void)
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{
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DAC1->CR &= DAC_CR_WAVE1;
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DAC1->CR &= ~DAC_CR_TEN1;
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DAC1->CR |= DAC_CR_BOFF1;
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DAC1->CR |= DAC_CR_EN1;
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}
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static void MODEM_LL_ADC_TIMER_INITIALIZE(void)
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{
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/* 72 / 9 = 8 MHz */
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TIM2->PSC = 8;
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/* enable DMA call instead of standard interrupt */
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TIM2->DIER |= TIM_DIER_UDE;
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}
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static void MODEM_LL_DAC_TIMER_INITIALIZE(void)
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{
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/* 72 / 4 = 18 MHz */
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TIM1->PSC = 3;
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TIM1->DIER |= TIM_DIER_UIE;
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}
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static void MODEM_LL_BAUDRATE_TIMER_INITIALIZE(void)
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{
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/* 72 / 4 = 18 MHz */
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TIM3->PSC = 3;
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TIM3->DIER |= TIM_DIER_UIE;
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}
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#define MODEM_LL_ADC_SET_SAMPLE_RATE(rate) (TIM2->ARR = (8000000 / (rate)) - 1)
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#define MODEM_LL_DAC_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
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#define MODEM_LL_BAUDRATE_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
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#endif
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#endif /* DRIVERS_MODEM_LL_H_ */
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